A large amount of activity in the microelectronics industry is directed toward developing methodologies for testing die on a wafer similar to the testing that is performed on a single chip package. Presently, burn-in and performance testing are performed on die that have been mounted onto a single chip carrier.
Tests are also performed on each die in a serial fashion. Serial testing of dice on a semiconductor wafer site-by-site is a time- and capital-consuming process. This wafer test process also is often insufficient for capturing faults and must be followed by additional testing once the dice are packaged. This process, particularly when combined with a burn-in requirement, leads to many repeated tests being performed on each die. Furthermore, dice are typically packaged before being thoroughly tested which adds cost to the final product because bad dice are not detected until the manufacturing process has been completed. In addition, problems in the manufacturing process or with the equipment used during manufacturing are not detected until the dice have been packaged and tested. As a result, numerous defective dice may be produced before problems with the manufacturing of such dice have been detected.
This problem is exacerbated because many companies that manufacture wafers send the wafers off shore to be packaged. When the packaged dice are returned, they are tested to determine whether the packages are acceptable. There may be a six-to-twelve week lag between the manufacturing of the dice and the packaging and testing of the packaged dice. Therefore, it may be several weeks before a problem is detected in the manufacturing process.
Testing dice on a wafer is difficult because of the large number of input/output (I/O) ports to be tested for the combined number of dice. It is difficult to form connections with each I/O on each of the die at the same time. Further, the electrical environment for making connections is poor. As a result, it is difficult to provide and receive data from even a single die at a rate greater than 50 to 60 MHz.
In addition, a large amount of thermal energy is produced when a large number of dice are operated at the same time. For example, if the wafer includes several hundred dice, each die can consume between 1 and 30 watts or more of power during operation. Further, if a die under test is shorted, the test probes could be destroyed when current is applied to the die.
It is an object of the present invention to solve these problems by using a wafer probe to test an entire wafer in parallel while minimizing test equipment costs and simultaneously providing a means for burn-in of dice on the wafer. It is another object of the present invention to provide current control to shorted devices in the parallel test environment. It is another object of this invention to enable "iddq" testing. It is still another object of the present invention to test the electrical performance of the dice using a combination of wafer fixturing and test methodology.